The present invention relates to high-performance metal oxide semiconductor field effect transistors (MOSFETs) for digital or analog applications, and more particularly to MOSFETs utilizing carrier mobility enhancement from substrate surface orientation.
In present semiconductor technology, complementary metal oxide semiconductor (CMOS) devices, such as nFETs (i.e., n-channel MOSFETs) or pFETs (i.e., p-channel MOSFETs), are typically fabricated upon semiconductor wafers, such as Si, that have a single crystal orientation. In particular, most of today""s semiconductor devices are built upon Si having a (100) crystal orientation.
Electrons are known to have a high mobility for a (100) Si surface orientation, but holes are known to have high mobility for a (110) surface orientation. That is, hole mobility values on (100) Si are roughly 2xc3x97-4xc3x97 lower than the corresponding electron hole mobility for this crystallographic orientation. To compensate for this discrepancy, pFETs are typically designed with larger widths in order to balance pull-up currents against the nFET pull-down currents and achieve uniform circuit switching. pFETs having larger widths are undesirable since they take up a significant amount of chip area. On the other hand, hole mobilities on (110) Si are 2xc3x97 higher than on (100) Si; therefore, pFETs formed on a (110) surface will exhibit significantly higher drive currents than pFETs formed on a (100) surface. Unfortunately, electron mobilities on (110) Si surfaces are significantly degraded compared to (100) Si surfaces.
As can be deduced from the above, the (110) Si surface is optimal for pFET devices because of excellent hole mobility, yet such a crystal orientation is completely inappropriate for nFET devices. Instead, the (100) Si surface is optimal for nFET devices since that crystal orientation favors electron mobility.
In view of the above, there is a need for providing integrated semiconductor devices that are formed upon a substrate having different crystal orientations that provide optimal performance for a specific device. A need also exists to provide a method to form such an integrated semiconductor device in which both the nFETs and the pFETs are formed on a silicon-on-insulator substrate having different crystallographic orientations in which the semiconducting layers that the devices are built upon are substantially coplanar and have substantially the same thickness.
One object of the present invention is to provide a method of fabricating integrated semiconductor devices such that different types of CMOS devices are formed upon a specific crystal orientation of a silicon-on-insulator (SOI) substrate that enhances the performance of each device.
Another object of the present invention is to provide a method of fabricating integrated semiconductor devices such that the pFETs are located on a (110) crystallographic plane, while the nFETs are located on a (100) crystallographic plane of the same SOI substrate.
A further object of the present invention is to provide a method of integrating SOI technology with CMOS technology using simple and easy processing steps.
A still further object of the present invention is to provide a method of fabricating an integrated semiconductor structure in which both CMOS devices, i.e., pFETs and nFETs, are SOI like.
A yet further object of the present invention is to provide a method of fabricating an integrated semiconductor structure comprising an SOI substrate having different crystal orientations in which the semiconducting layers that the devices are built upon are substantially coplanar and have substantially the same thickness.
The inventive method, which achieves the above-mentioned objects, begins with fist providing a structure that includes a carrier wafer and a film stack comprising at least a first semiconductor layer of a first crystal orientation and an overlying second semiconductor layer of a second crystal orientation which differs from the first crystal orientation. This providing step includes forming a substrate that includes the first semiconductor layer and the carrier wafer and then bonding at least the second semiconductor layer to the first semiconductor layer.
An opening, i.e., trench, is then formed into the structure mentioned above which exposes a portion of the first semiconductor layer. A semiconductor material having the same crystal orientation as the first semiconductor layer is epitaxially grown in the opening on the exposed surface of the first semiconductor layer. Spacers are typically formed on the exposed sidewalls of the opening prior to forming the semiconductor material. An insulator layer is formed atop the structure and a handling wafer is bonded to the insulator layer. The resultant structure is flipped, top to bottom, and the carrier wafer is removed exposing the first semiconductor layer. The exposed first semiconductor layer is then removed and a portion of the previously grown semiconductor layer is etched back to provide a structure in which the semiconductor material having the first crystallographic orientation is substantially coplanar and of substantially the same thickness as that of the second semiconductor layer.
At least one nFET and at least one pFET may then be formed on either the second semiconductor layer or the semiconductor material depending on the surface orientation of that layer. Both CMOS devices, i.e., the nFET and the pFET, are SOI like devices since that are formed in an SOT layer, i.e., the second semiconductor layer or the regrown semiconductor material, that is separated from the handling wafer by the insulator layer.
The present invention also provides a method of fabricating a uniform strained-silicon-direct-on-insulator (SSDOI) structure across a wafer that has different crystal orientations for nFETs and pFETS. The SSDOI structure is made using processing steps similar to those described above. In the SSDOI embodiment, graded SiGe alloy layers and strained Si layers are used.